-
It's a shame that such a great idea for a simple hdl parser which isn't tied into a larger bloatier package of tools and keeps within the simple scripting framework of the very popular scripting langu…
-
-- this entity
entity mux2t1 is
Port (A,B : in std_logic_vector(7 downto 0);
SEL : in std_logic;
MUX_OUT : out std_logic_vector(7 downto 0));
end mux2t1;
-- gets copied as …
-
See [build #4](https://travis-ci.com/Matthewar/ASV/builds/78376197)
Input: "OF\241\ENQ"
-
**What is your question?**
Sometimes I run VSG against code that does not compile i.e. it has VHDL syntax errors. VSG tends to fall over in a heap. Should this happen? Are there not traps somewhere s…
imd1 updated
6 months ago
-
I am curious on your thoughts in allowing pyVHDLModel to be used in analyzing partial (missing files) or mixed language projects. Currently, the Analyze function in `__init__.py` will raise an excepti…
-
Hi there,
I was wondering if there is an option where I can force vhdl-linter to lint only the file that is open within vscode.
At the moment I am using vhdl-linter mainly for semantics, over a …
-
I found setjmp/longjmp are used widely in parsers.
valgrind reports the memory leaks related to them.
I guess longjmp is trigged when reading unexpected EOF.
Incomplete source code may make memory lea…
-
Great tool!
Would you be willing to provide a way to pass a list of files instead of a folder for lining?
It is a more useful mode for integration into a build system.
-
The integer modulo (remainder) Operator "%" insn't implemented...
Demo code:
```cpp
#include "intN_t.h"
#pragma MAIN_MHZ test 100.0
int32_t test(int32_t a, int32_t b){
return a % b; /…
-
Having an open source toolchain for synthesizing integrated circuits can be really useful for research projects. However, some industries enforce the use of vhdl, which is not highly supported by open…