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As the title says, inactive FPGAs' ILAs get garbage data in the topology test. For instance, FPGA 0 from the fully connected 3 node topology is active in the test and has the following as the first fe…
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### Question
My Project requires a huge image > 140GB. We are programming FPGAs and the tools required for that are sadly that large.
My current Setup:
I've got a local registry which contains th…
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Hi,
I have been running a simulation in Vivado. Writing into the BRAM of 16 KB through PCIS is taking more than 2 hours. I need to write more than 10 BRAMS. If it takes time like this, I am worryin…
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I'm getting an error message when building `static` application for `u250`. I run the following command
```
cmake ../CMakeLists.txt -DFDEV_NAME=u250 -DEXAMPLE=static
```
### Error Message
```
…
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I downloaed this repository, and build it following the readme.md
During systhesis, an error occured as following:
axi_dynclk_S00_AXI.vhd and axi_dynclk.vhd are not found in EBAZ4205_SDR_spectrum-…
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in Vitis can't build project:
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
WARNING: [VPL 60-1142] Unable to read data from '/home/zhr/Project/dpu_vitis1/alinx_9eg_system_hw_link/Hardware/dpu.build/link…
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Hi Taichi,
Thanks for taking care of this project! I am trying to compile it with Vivado, but I have some problems with Xelab, so I need some help.
More specifically, I tried these versions and …
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CI/CD with travis-cd, [https://github.com/Viq111/Vivado-CI](https://github.com/Viq111/Vivado-CI)
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## USB no response after cable plug in
- change to another usb port (back port on mother board is the best if PC)
## normal driver status
![image](https://github.com/user-attachments/assets/14b2164…
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