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I implemented RISCV SoC on a Zcu102 fpga. I am trying to use openOCD and jtag-hs2 to download code to the board as instructed in the README. Does anyone know what could potentially cause this error an…
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Looks like JTAG boundary scan fails to find the ARM core on Kasli SoC.
* Kasli-SOC v1.1.1
* Ubuntu 2022.04 LTS
* Ubuntu AppArmor disabled
* [Incremental build](https://m-labs.hk/artiq/manual/bu…
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This is an inquiry to the wider audience who are working on getting NVDLA running on a FPGA platform--we'd like to share what we are doing and check progress on other groups out there .
we are putt…
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I'm facing an issue in mounting usb formatted in ntfs. Kernel 4.13 in antergos with gnome.
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Hello,
I am currently assessing the available secure boot modes of the Polarfire, and did the following test in SoftConsole:
- built project "mpfs-gpio-interrupt" in "LIM-Release" build configurat…
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I successfully booted Linux with FPU disabled. When I enable FPU, I get the following errors:
```
[ 0.156632] smp: Bringing up secondary CPUs ... …
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I am seeing intermittent detection of the octo card between boots, and random channel assignment within each iteration of speaker-test utility.
Note during these tests the hardware is sitting in is…
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Hi,
I noticed your extended CEDR on RISC-V Heterogeneous SoC Design. I wonder if the RISC-V integrated CEDR source code along with the FPGA image is available? I hope to conduct some DSE experiment…
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_From @dhslichter on September 25, 2017 22:40_
NIST has some interest in an EEM TDC module (currently code-named Stamper), and I'd be interested in getting some draft specs based on potential use cas…
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I would like to follow progress / news (https://balthazar.space/wiki/News) via RSS-Feed in my feed reader. Could you please add this?
I tried to contact you via email about this matter without succ…