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Please can you help how can i set Intel(R) Arc(TM) A770M as default that sycl-ls instead of Device Name: Intel(R) Iris(R) Xe Graphics
As **llama-cpp** is detecting Xe Graphics and running inference t…
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Issue Type: Bug
Extension Name: fpga-support
Extension Version: 0.2.6
OS Version: WSL2 Ubuntu x64 20.04.5
VS Code version: 1.76.0
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Can you consider to implement generic uio in your python periphery? As i see your MMIO implementation can serve the reg mapping for a /dev/uioX, only the IRQ waiting which is needed to implemented for…
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**Brief introduction of the Arrow Chameleon96 board (https://www.96boards.org/product/chameleon96/):
This board is a Cyclone V board (same chip as de10-nano) but FPGA was considered secondary and Nov…
somhi updated
3 years ago
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I am trying to build FemtoRV petitbateu but it fails to build two different ways for two different toolchains.
When I build with yosys+nextpnr using command: `python3 -m litex_boards.targets.digile…
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### Summary
We've observed that Fastino occasionally fails to initialise properly on power-up.
Our suspicion is that the bitstream is not being read correctly because the power-up sequencing fo…
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Hi, I'm working on the Butterstick FPGA dev board, in DFU mode. I can get all the way to a successful flash onto the FPGA, as indicated by a blue LED chaser effect on the board. However, once there, t…
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# Tutorial for SymbiFlow with embedded RISC-V
# Brief explanation
Write a tutorial for getting started with SymbiFlow on an embedded RISC-V CPU on a small FPGA with Zephyr.
## Expected result…
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Hello Howard,
Many thanks for your Cyclone 5 tutorials they have been a great help.
I have been looking at your interrupt example and have successfully run it on the Arrow Sockit board. However I am…
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Good day,
I have Sipeed Tang Nano 1K (which is replacement for Tang Nano already supported in Litex) with GW1NZ-LV1QN48C6/I5 and BL702 usb-jtag
Here's its documentation https://wiki.sipeed.com/h…