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There are currently 2 differents way used to test DRC assertions in the recent [PRs](https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_pv/pulls):
- DRC check functions like [`.width`](ht…
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## Expected Behavior
when the gf180mcu_fd_io__bi_t.cdl is run on ngspice by making the necessary connections of the pins to configure it to IE mode and drive a PULSE signal on PAD and plot output on …
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## Expected Behavior
ppolyf_u_2k_6p0 has a sheet resistance of 2k/square.
## Actual Behavior
The resistance is much lower than this (68 ohm).
This is also true for the other ppolyf resisto…
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If the intent was to follow the standard used by the sky130 PDK, then this is an epic fail. It needs correcting on multiple fronts.
For starters, the standard cell verilog modules make references …
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It seems that the precheck runs out of memory during klayout check causing the following traceback when being run on github actions:
```
{{STEP UPDATE}} Executing Check 3 of 4: Klayout BEOL
Traceba…
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**mpw_precheck** should have support for selecting different PDK and validate user project based on gf180mcuC.
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The precheck jobs came up with the following failure:
```
{{FAILURE}} 3 Check(s) Failed: ['Klayout FEOL', 'Klayout BEOL', 'Klayout Offgrid'] !!!
```
See the logs on https://github.com/proppy/carav…
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When starting klayout, the following error is raised when gdsfactory is not installed causing the pcells not to load:
```
ERROR: /home/proppy/silicon-2-env/share/pdk/gf180mcuC/libs.tech/klayout/tech…
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As circuits become more complex is important to check that your design intent matches the produced layout
TODO:
- [ ] net-tracing in klayout for generic [tech](https://github.com/gdsfactory/gdsf…