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## Questions
- Trace simulator **examples**/documents
- Want to be able to count resources for qram queries only.
- What optimizations if any have been implemented where?
- Simulators?
- Co…
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Is it possible to add support for building asynchronous circuits and also provide some tutorial on how this can be done on Chisel.
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### Expected behavior
The property `QuantumTape.diagonalizing_gates` always either returns the correct diagonalizing gates or raises an error (warning) if they are unknown.
### Actual behavior
When…
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Implement all Primitive Operations in Firrtl [spec](https://github.com/freechipsproject/firrtl/blob/master/spec/spec.pdf)
Then we can parse firrtl, dynamically build the circuit by components, then w…
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The SymbiFlow project is centered around the support for various FPGA technologies. Many projects that constitute SymbiFlow are not directly related to hardware, however they still might require some …
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When the input of a VCVS is zero for a very large circuit, the circuit slows down drastically.
Example:
https://tinyurl.com/y3zxq8on
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Hello :wave: Cool project!
I just wanted to ask what is planned for the Verilog generation in the TODO section of the README? I'm a Verilog RTL developer and would be keen to contribute to this pro…
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In the docs for the driver "If the sel input is high, the output is set to the input value." however I have found that if sel is high and input is high-Z the driver outputs 1 instead of high-Z
This…
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Hi Stewart,
I love your work. Happy anniversary for Q.js!
When run XHHH in your live editor, the results make sense to me. But the results you give are inconsistent with results of other simulat…
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Not sure if this was brought up before or not, but when you input 480i signal, while scanlines and bob deinterlace are both on, scanlines doesnt seem to turn off automaticly, creating an image with ch…