-
I'd like to be able to translate the migen Module hierarchy into the exported HDL hierarchy at least to some extent.
* This would allow estimating resource usage at some useful granularity.
* It w…
-
The following migen snippet:
```
If((self.addr == 0x18a) and (self.joy_enabled == 1),
```
produces the following Verilog:
```
if ((addr_1 == 9'd394)) begin
```
-
- [X] yosys
- [x] nextpnr
- [x] prjtrellis
- [ ] prjxray
- [ ] yosys-symbiflow-plugins (blocked by https://github.com/SymbiFlow/yosys-symbiflow-plugins/issues/20 and https://github.com/SymbiFlow/y…
FFY00 updated
4 years ago
-
@petut - any chance you or any of your contributors are Uni students?
If so, I would love to see a MigenAXI/Zynq intergration proposal as part of the [Google Summer of Code](https://summerofcode.wi…
-
@bunnie has been working with LiteX / Migen recently and mentioned he thought following issue would be a big source of bugs in LiteX / Migen designs. I would like to get @sbourdeauducq 's (and others)…
-
Consider this minimal example:
```python
from migen import *
from migen.fhdl import verilog
class my_module(Module):
def __init__(self):
self.input = Signal(8)
self.outp…
-
I am trying to run
```bash
./make.py --board=arty --cpu-count=1 --build
```
and am met with the following error:
```bash
[error] java.lang.ClassNotFoundException: vexriscv.demo.smp.VexRiscv…
-
Add good support for nmigen.
-
hi! I friend of mine challenged me saying that if LiteX/nMigen makes things so easy, I should be show him an example of a led blink project in less than 10 lines. I did that, as follows:
```
from …
-
Hi!
We are working on getting the panologic-g2 into the [`timvideos/litex-buildenv`](https://github.com/timvideos/litex-buildenv/pull/223) repository and [`litex-hub/linux-on-litex-vexriscv`](https…