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FDIV and FSQRT rounding mode calculation mismatches found when comparing the results from FPnew to a RocketChip RISCV IMAF processor.
I have attached a few examples of calculation mismatches found:…
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# Abstract
The binary that is flashed via the rust example is over 250MB large, too large for the target system. The C example does NOT suffer from this issue.
# Reproduction
1. Get Rust versio…
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### Answers checklist.
- [X] I have read the documentation [ESP-IDF Programming Guide](https://docs.espressif.com/projects/esp-idf/en/latest/) and the issue is not addressed there.
- [X] I have updat…
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* [RISC-V toolchain on OSX](https://github.com/riscv/homebrew-riscv) rv64 by default and it doesn't work for picorv32
* to have rv32, please install [riscv-gcc](https://github.com/riscv/homebrew-risc…
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For RV32, mstatus will be set to 0x5 0000 0000 in processor_t::reset().
It's not reasonable.
Refer to 3.1.8, Privileged Architecture Version 1.10:
For RV32 systems, the SXL and UXL fields do not e…
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Im not sure if I can do this with spike. I make a hello world and compile in 32 bits like you see below and I tried to measure the machine cycles:
#include
#define read_csr(reg) ({ unsigned lo…
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I have the following error:
../riscv/insns/fmac_s.h: In function ‘reg_t rv64_fmac_s(processor_t*, insn_t, reg_t)’:
../riscv/insns/fmac_s.h:12:19: error: ‘READ_RD’ was not declared in this scope
…
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I have a question regarding which bits in the SIP CSR is write-able. According to the Spike implementation, only Supervisor Software Interrupt Pending could be set for the SIP CSR.
https://github.…
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I have been playing with riscv-formal for checking one of our small processors, and I came across a few issues where the documentation does not appear to match what the checks are actually doing. Our …
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The following are closely related:
- SoC design, peripheral integration
- processor reference manual
- device drivers
- platform init / boot flow
Given a [declarative language for modeling an…