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I modified the file rocket-chip/src/main/scala/system/Configs.scala
I've added a line: `class MyConfig extends Config(new WithJtagDTM ++ new DefaultConfig)`
Then i launch in rocket-chip/emulator `ma…
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richard@richard-HP-ENVY-15-Notebook-PC:~/Rocket/rocket-chip$ cd emulator richard@richard-HP-ENVY-15-Notebook-PC:~/Rocket/rocket-chip/emulator$ make debug cd /home/richard/Rocket/rocket-chip && java -X…
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Hi, I am new to vivado, I made some changes to dcache in rocketchip, now I want to run riscv program in simulation to verify if there is any problem with my design, but I got a lot of errors when I tr…
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Hi,
I am new to rocketchip and am trying to run a helloworld using emulator.
I am getting the error and the system is halted.
Error:
"tohost and fromhost symbols not in ELF; can't communicate with…
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the issue metioned on:
https://github.com/litex-hub/linux-on-litex-rocket/issues/40#issue-2324887509
i found the arty.dts had a node with interrupts-extended:
```
L1: interrupt-controller@c0000…
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hi,你好。 我最近也用chisel做了一个加速器,也是rocket+加速器 的模式,然后目前跑了verilator 程序仿真了。 下面我想做功耗仿真,我看到其他论文里面有类似这种图:
![image](https://user-images.githubusercontent.com/17881739/82857954-0db8dc00-9f45-11ea-9bb0-9232d4e0c8c8.…
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**Type of issue**: bug report
**Impact**: FPGA Building
**Other information**
lore@Helium:~/src/rocket-chip/vsim$ make verilog CONFIG=DefaultFPGAConfig
mkdir -p /home/lore/src/rocket-ch…
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When running yosys -p "read_verilog -sv generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.sv"
on my newly generated System Verilog code, after finally extending Yosys for the new syntax…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/firesim)
- [X] Yes, I searched [prior issues](https://github.com/firesim/firesim/issues)
- [X] Yes…
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IMDCE has special handling for certain annotations that is considers "weak", I believe regarding their use of the hierpath symbol.
This is only done for ports, and should be extended to other place…