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Hi,
Can you check please why do we need this `ifdef statements in
design/pic_ctrl.sv file of the swerv DB?
Now I'm getting similar (?) error for our new cores
in memories preloading code :
"…
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Hi all,
I've been interested in running some tests on the SweRVolf, and have been succesfully programming it within the RAM region (0x00000000-0x07FFFFFF) and the DCCM region (0xF0040000-0xF004FFFF…
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Hi,
I'm trying to add adxl362 accelerometer support to Zephyr. the accelerometer is connected to SPI1 via multicon and is working ok using an ASM program.
However, when trying to compile, using wa…
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Hello,
I am using the swerv RTL and a mixed uvm + C environment to test out my firmware code. I generally write my test and cross-compile the c code to generate the object file and further generat…
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Hi,
I am using following doc to build tool-chain
https://riscv.org/wp-content/uploads/2015/02/riscv-software-stack-tutorial-hpca2015.pdf
at slide 18, it is mentioned to Generate RV32 code.
Tryi…
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Hi,
I tried running ssp by following the instructions given in README.md as follows:
1- git clone https://github.com/Codasip/SweRV-Support-Package-free.git
2- cd SweRV-Support-Package-free/
3- p…
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Hi,
I have a Nexys A7, the successor of the Nexys4DDR (according to the manufacturer, the boards are almost the same).
I installed Vivado 2018.2, took the 1.5 SweRV core, changed the strings ask…
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I notice that your branch target buffer is a Register file, which have no read latency. So I got two question:
Is this a usual way to use Register file as BTB rather than use a block of sram?
And …
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Can someone help me understand this snippet of code from `dec_tlu_ctl.sv`? I am not familiar with the naming convention of the SweRV core either, so I would also appreciate if someone can enlighten me…
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// file "decode" is human readable file that has all of the instruction decodes defined and is part of git repo
// modify this file as needed
// to generate all the equations below from "decode" e…