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ultraembedded
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biriscv
32-bit Superscalar RISC-V CPU
Apache License 2.0
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Boot RISC-V Linux Failed, ERROR: Invalid opcode: 30529073 at PC: 8040016c
#25
RonxBulld
opened
11 months ago
0
Wrong opcode for CSR_MCYCLE, CSR_MTIME and CSR_MTIMEH
#24
Gianluke27
opened
11 months ago
0
FPGA Implementation
#23
SB308
opened
11 months ago
0
undefined reference to `VlThreadPool::VlThreadPool(VerilatedContext*, unsigned int)'
#22
samuelyenyen
opened
1 year ago
1
Division by 0
#21
CrazybinaryLi
opened
1 year ago
0
make failed...error
#20
crayon7442
opened
1 year ago
1
Operating Frequency
#19
anandmay22
opened
2 years ago
1
Consider taping out core on SKY130 open source process with no cost shuttle program?
#18
mithro
opened
2 years ago
0
Consider adding biriscv to LiteX CPU ecosystem?
#17
mithro
opened
2 years ago
0
LWGP
#16
altuSemi
opened
2 years ago
0
about Branch target buffer
#15
cool-ic
opened
2 years ago
2
Linux compatibility
#14
JOHNTBIJU
closed
2 years ago
1
link library for biriscv
#13
riya1407
opened
2 years ago
0
JTAG Debugging Request
#12
nvitya
opened
3 years ago
0
Benchmark scores
#11
kuopinghsu
closed
3 years ago
6
Not an issue, rather a request
#10
bhawandeepsingh
opened
3 years ago
0
How initializa the memory from the verilog
#9
emiliofmc7
opened
3 years ago
0
TCL file for FPGA build
#8
alaasal
opened
3 years ago
1
Questions Biriscv
#7
emiliofmc7
opened
3 years ago
0
enable write to MTIME
#6
altuSemi
closed
3 years ago
0
DEBUG interface
#5
zhuzhizhan
closed
4 years ago
2
Using own ELF results in an infinite loop
#4
MakisChristou
opened
4 years ago
5
How to use my own test programs?
#3
hyf6661669
closed
4 years ago
2
Bug: Core should fault on misaligned branch source instruction, not on the target.
#2
ultraembedded
closed
4 years ago
0
Bug: 'csr_swap' type operations on SATP register do not work
#1
ultraembedded
opened
4 years ago
0