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Addition of a comprehensive top-level verification environment for the design.
The steps to be followed:
1) Make a diagram of this verification environment indicating the placement of components inc…
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Hello.
hdlConvertor does not support the parallel_case attribute. An example can be found here: https://github.com/KatCe/hdlConvertor_issue_185
Using the python script in the repo I tried all 3…
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Opening Settings -> Editor -> Code style -> System Verilog hangs forever. This means you can't edit the coding style at the moment.
igmar updated
5 years ago
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Hi Team,
we installed rocket tools and chisel in machine and set the path, when we run the cmd "make verilog" in rocket-chip we are geeting attached error. Can you help me on this issue please
…
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### What's hard to do? (limit 100 words)
Currently when choosing between the DSLX interpreter, the IR interpreter, the JIT or a Verilog simulator to run a set of DSLX tests: developers have to go thr…
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Slowly making replacements for the Qucs Verilog-A Library devices.
1) Modded VCR.sch to get rid of divide by zero if Vin=0 volts. What actual VCR is chosen is TBD.
2) A new mod-amp was created usi…
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`VerilogTranslationPass` fail with the following example.
```
def mk_aType(a: int = 4, b: int = 6):
return mk_bitstruct(
"aType",
{
"a": mk_bits(a),
…
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APIO is a great utility and I use it frequently for testing my Verilog designs.
Are there any plans to support SystemVerilog?
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Hi Vitor,
Many thanks for your excellent work on this plugin! I was trying it, and saw that sv structs and class still can't do autocompletion. I saw issue #150 is still open and got to wonder if t…
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Hello everyone!
When I am trying to build the project I get the following error:
```
1 targets failed
emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].ge…