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### Feature Description
I'd like bundles between modules to be connected using more terse Verilog when there's no modification of the bundles.
### Type of Feature
- code cleanup
### Related…
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On `master`, using GHC 9.6.2, I'm seeing:
```
$ cabal run clash-testsuite -- --no-vivado -p IntegralTB.SystemVerilog
Warning: Requested index-state 2023-06-17T22:28:17Z is newer than
'head.hacka…
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## My Environment
I wish to create a logic simulation environment while using ibex as a core. I have a question related on the structure of the core though.
1. Besides manual modific…
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Emits a Verilog (or other) mapping from tag to full hierarchical signal path. The intent is to allow people writing more traditional Verilog or SystemVerilog testbenches to better hook into Chisel DUT…
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Hello people, i was here trying to run a few files and gate level with time zero delay and i depared with theses messages:
- Sorry: ifnone with an edge-sensitive path is not supported.
example : …
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I'm at a loss of how to get started using this tool. There are so many conflicting linting rules that I don't know where to go.
Is there a sensible default configuration that can be shared and lin…
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Some time ago I opened a discussion about creating truly common middle-level HDL/representation, see the https://github.com/SymbiFlow/ideas/issues/19
It would be nice to hear your opinion, maybe ev…
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Bluesim self-checking testbenches using `dynamicAssert` wind up exiting with status 0 whether they pass or fail. This makes them difficult to integrate into conventional test frameworks (or, for that …
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I wrote a [RISC-V processor](https://github.com/jeras/rp32) in heavy SystemVerilog with a lot of:
* arrays, `struct`ures, `union`s, `typedef`s, `enumeration`s, custom type `parameter`s, ...
* assign…
jeras updated
2 years ago
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Dear all
I'm not sure, whether it is appropriate to file my problem as a GHDL bug report, as it may originate from vendor side...
First of all, I appreciate GHDL as a very useful tool for FPGA d…