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Hello guys,
i was using verilator for dumping some traces (VCDs).
i found out that is does not support the following VCD format
```
....
$var port [31:0]
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Hi,
I'm thinking about adding support for SVA properties to Yosys. However, it is pretty hard to do that without a simulator to test against. So I've tried all the free and free-as-in-free-beer Veril…
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It would be very usefull, to add bluesim as simulator, since it compiles the bsv code directly into an executable (bsv → c++ → asm). That increases the simulation speed, which is currently the lar…
Febbe updated
7 months ago
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The original issue I brought up several years ago was that AUTOINST would sometimes include bit slices for ports that were signed and cause tools like DC to give warnings about signed to unsigned conv…
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@rdaly525 I fetched the upstream of coreir, checked out dev and tried to build the testbench with a new floating point test, but when I did ```make test``` I got a testbench failure. The output is bel…
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Consider this minimal example:
```python
from migen import *
from migen.fhdl import verilog
class my_module(Module):
def __init__(self):
self.input = Signal(8)
self.outp…
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**Describe the bug**
The Verilog Editor vertical scrollbar is not functioning properly.
No horizontal scrollbar.
On writing/copying long codes which has more lines than the view-port can offer, the…
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See https://github.com/ra3xdh/qucs_s/discussions/681 for context. The ideal transmission line has TRAN model. It's need to implement similar for miscrostrips. Contribution is welcome here. Could be a …
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- [ ] in the Bluespec simulator and
- [ ] via the Verilator backend build
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Check whether or not following tools support generated CSR modules/RAL packages.
* Simulation
* Cadence Xcelium
* VHDL output
* Mentor Questa/ModelSim
* Aldec Riviera-PRO
…