-
While the [README.md](https://github.com/vortexgpgpu/vortex/blob/15ca8290d0c3cfcc559e78cec98d87172c7e6719/README.md?plain=1#L20) mentions U250 as a supported FPGA, it seems Alveo U200 is supported at …
-
Hello. I try to reproduce the Xilinx 7-series routing architecture data in this paper. However, I cannot find the .json file about Xilinx 7-series FPGA architecture in this repository. Only one exampl…
-
How much work is required to set up development on Xilinx FPGAs? What is the status of the project vis-a-vis Intel's Clang SYCL? Is there a chance of Intel's SYCL compiling to Xilinx FPGAs? What is th…
-
I am having a trouble in generating the bitstream file xclbin from the exported RTL file I did from Vitis HLS, I am using the command prompt executing this 'v++ -l --platform /home/centos/aws-fpga/Vit…
-
After modifying the Makefile PATH for vivado, it works for the previous issue but soon have another.
Please help for any hint.
vivado -mode batch -source tcl/run.tcl
****** Vivado v2018.3…
-
At the moment, it seems Logisim-evolution is only supporting target FPGA synthesis tools from Xilinx and Intel (Xilinx ISE, Xilinx Vivado, Intel Quartus Prime). The low-cost, open-source TinyFPGA BX b…
-
### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Ok so basically, I need to use CVA6 to add a peripheral to it. For that I want to open …
-
Hi, I've passed the C simulation and C synthesis, but it took too long time(about five days) to finish the C/RTL cosimulation. So I dropped the cosimulation and wanted to export the RTL , but now I g…
-
- [x] Triggering based on custom Verilog in FPGA
- [x] Xilinx interrupt controller configuration on C code side
- [ ] #349
- [ ] #350
-
### Description
I do not have a VM running Ubuntu, I only have a Container.
I don't have ivado installed in the container, but I do have Vivado running on CentOS.
I'd like to generate all the Viv…