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Hi,
I'm trying to run Vitis AI trace on the resnet50 application, but for some reason, there is no **summary.csv** and **xrt.run_summary** files generated.
I'm using Vivado flow, DPU IPv 4.1, Petali…
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It seems the current version of verilator doesn't support module like this:
```
module via (.a(w), .b(w));
inout w;
wire w;
endmodule
```
There was a discussion
https://forums.xilinx.com/t5…
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I used the automated make script to generate a Vivado project for FPGA implementation of Vortex. It creates the project however gives error during synthesis:
> [Synth 8-2671] single value range is …
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I think my problem is similar to #11 , but the solution from there isn't working for me.
I want to boot from my SD card with Linux that I generated using Enclustra BSP and see the U-boot UART conso…
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Hi, I'm working on the step 4: Compile the overlay project on Vivado 2022.2, ubuntu 20.04. And the kria-vitis-platforms branch is [xlnx_rel_v2022.1].
When it comes to the command `source -notrace .…
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I am using the latest GHDL from github.
I built unisim with
```
compile-xilinx-vivado.sh --unisim --source /tools/Xilinx/Vivado/2022.2/data/vhdl/src
```
then I ran
```
ghdl -m -g -Pxilinx-v…
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Hey all,
Wondering if anyone has run into this issue when running `make all` or `make sdcard` from within the project topdir inside the Docker container. **The only thing I'm doing differently is t…
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Hi!
I'm using 3.12.2 python; 2.3 fusesoc and 2021.1 vivado.
I tried running these commands:
`fusesoc run --target=sim barvinn `
`fusesoc run --target=synth barvinn`
but i got these erro…
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I'm using Vivado 2023.1 and the call to the vivado batch file to see version fails. It doesn't appear that the current vivado.bat file handles the -version parameter.
-------------------------
Ex…
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Hi, I've passed the C simulation and C synthesis, but it took too long time(about five days) to finish the C/RTL cosimulation. So I dropped the cosimulation and wanted to export the RTL , but now I g…