-
I managed to compile ghdl (master) in WSL using gcc4.9 and gcc5. When executing the adder test in cocotb, the following canbe seen:
```
make results.xml
make[1]: Entering directory 'cocotb/examples…
-
I was trying to generate coverage report with Vunit, Python, Questasim. With the older release of Vunit I was able to generate Coverage report for module under test (and not the test bench coverage re…
dsp20 updated
5 years ago
-
ModelSim PE Student Edition is only available for Windows.
I couldn't find a (free) ModelSim setup file for Linux except ModelSim-Altera Edition. Is it OK to use it?
-
Hi, the documentation speaks of the possibility to build either with the gnu riscv toolchain or the eth compiler...
In fact, I was not able to get anything completed with the gnu toolchain (-march=…
-
I discovered an issue today while trying to simulate a medium-sized project (several files) which uses SystemVerilog packages for constant and property definitions; it complained about multiple declar…
-
Hi, I just downloaded the latest version of your code base and tried to run "make run-asm-tests" and I end up with the following error:
>[TRACER] Output filename is: trace_core_00_0.log
>** Fat…
-
Hi, I am getting the following issue while running dhrystone in questasim 10.6 :
![i…
-
I've followed the instructions to run the simulation: clone, update-ips, source vsim.sh, run make clean lib build opt. At some point during make I get an error `Error: cannot find "/opt/intelFPGA/17.1…
lstrz updated
5 years ago
-
ashan@e420:~/git/pulp/pulpino/sw/build$ make helloworld.vsimc
[ 0%] Built target bench
[ 0%] Built target crt0
[ 0%] Built target string
[ 25%] Built target sys
[ 25%] Built target Arduino_cor…
-
What is the command to generate .hex from .elf for Questasim?
I used the following command but not sure that is correct (just run few ISA tests and they worked fine but when I run rsort benchmark, …