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After update the database few days before, the test with VCS always fail in vsim directory, please help what should i try for the simulation:
platfort : 14.04.1-Ubuntu, with gcc 4.4 and gcc 4.8.4
c…
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[New to riscv and keystone]
I managed to compile and run busybear using qemu (upstream qemu 4.0.0, not riscv-qemu).
But when I was trying to run bbl, as documented in http://docs.keystone-enclave.…
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Hi there
I think there are some mismatches between riscv-formal and the spec (v`20190305-Base-Ratification`) with the `C` extension decoding.
- Some `C` instructions require that operand fields …
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Hello, I've been trying to install riscv-tools for a day or so without any luck. I'm working on Ubuntu 16.04 running on a Macbook using Parallels. Here is the output from the script:
Starting RISC-…
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Hi,
I'm new to the riscv tool chain and Ariane. I have installed the tools from [https://github.com/riscv/riscv-tools](url) and downloaded the master branch of Ariane, following the getting starte…
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I have an issue with building the boom-template verisim project, the make process fails and doesn't generate the binary target. I am new to this problem so perhaps I am just doing something wrong. It …
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Hi everyone from Hwacha team,
Thanks for sharing this template for Hwacha!, I'm starting to test your repository and after a cloning and building the default configuration (**ISCA2016Config**) the em…
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**Type of issue**: bug report
**Impact**: API modification
**Development Phase**: request
**Other information**
**If the current behavior is a bug, please provide the st…
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Big board, big FPGA, plenty of pins and PCB space.
DDR3 is great but some for some low-latency application SDRAM is still better.
Can you see if possible to add a 32-bit 64MB SDRAM on the next relea…
emard updated
5 years ago
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Thank you for the very useful repo. I'm new in RISC-V and I want to use rocc interface to evaluate my research. basically, I make a prototype for decimal multiplication that needs to evaluate through …