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Does there exists any tool/scripts which converts a given ModelSim/QuestaSim compile.do file into an run.py? I have some quite large Xilinx Vivado generated files, with vhdl and verilog (incl. Include…
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As far as I know, this should be perfectly valid VHDL, but GHDL is throwing an error with it.
```
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package reproduc…
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I was updating my commercial VHDL simulator installations, as I noticed that OSVVM is shipped in source and pre-compiled in Riviera-PRO, Active-HDL, ModelSim and QuestaSim.
Should GHDL do the same?…
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mac_streamer.sv line 76:
.tcdm ( tcdm.master[0:0] ), // this syntax is necessary as hwpe_stream_source expects an array of interfaces
modport definition for tcdm port is al…
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Hej
I'm not sure what the intention is: The compile tcl-scripts reference the sim directory for each part. This directory however is not in the repo in all cases.
I "fixed" that in some scripts by…
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Support was added to run the cocotb test cases using modelsim under windows in #408.
I noticed test case issue_142 fails when running modelsim 10.4c under windows7.
Here's the transcript when TOPLEV…
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I tried to implement a [compile script](https://github.com/UVVM/UVVM_Utility_Library/issues/1?ts=2) for [UVVM_Utility_Library](https://github.com/UVVM/UVVM_Utility_Library?ts=2). This library uses sha…
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make vcompile throwing error on axi_node as below
```
prasar00@i80studpc06:~/project/pulpino/sw/build:$make vcompile
Scanning dependencies of target vcompile
vlib: Command not found.
vlib: Comm…
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When trying the examples (e.g. `examples/dff/tests`) in VHDL mode with Questa as simulator by calling
`make SIM=questa TOPLEVEL_LANG=vhdl`, the test is executed, but finishes with an error:
~~~~
# …
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Hi,
I'm running the hello world simulation. It does not print "Hello world". Using Questasim 64.
The following warnings are shown:
# ** Note: (vsim-3812) Design is being optimized...
# ** Note: …