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Hello Furkan,
I'm new to lowrisc and I'm following your instructions to implement RISC-V on Zed.
I have these messages when I run make (verilog, vivado etc...)
```
alpha@alpha-VirtualBox:~/low…
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I built `bbl` with an smp-enabled `vmlinux` as payload. It runs well under `spike -p2`. But when I ran it in a multicore rocket chip on zedboard through `./fesvr-zynq bbl`, it failed with such a log:
…
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What is the target/achievable frequency for running the single core on FPGA?
I see from http://www.pulp-platform.org/documentation/ 654 MHz on 65nm ASIC, but no info for FPGA implementation.
I can a…
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I set the date for releasing ReconOSv4 for May 19th. However, despite the Vivado support, other improvements to include are not that clear.
Here is a random list of items i would like to be officia…
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Good Day,
So, I've posted to this list for help with my issue getting OP-TEE and Linux booting properly on a Zedboard. As my other post details, OP-TEE boots fine but Linux pukes during PLL init. I…
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Hi Brandon,
I send data from PS to the PL side by "axidma_oneway_transfer()", then the PS side process do nothing but waitting for an interrupt generate by gpio ip core in PL side, which indicate…
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Some features from the debug-v0.3 release should be merged to minion-v0.4 for better continuity. Such as the recent Zedboard port from Furkan.
Also a contributor files should be provided this time …
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Hello,
Is it possible to do an FPGA demo in a zynq ?
I got this error when generating a bitstream for the default fpga kc705:
```
source script/make_project.tcl
# set mem_data_width {128}
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I'm trying to use this layer to create an FSBL from an HDF file while building my image. I keep running into failures building the FSBL like this one:
>[ERROR] : Can't read file - /home/brett/Thes…
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Hello,
I'm doing an rtos port on RISC-V and currently working on the fpga-zynq/rocket-chip directory of Berkeley's.
Could you please provide instruction to how you used Vivado tools to generate…