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Hello Furkan,
I try to follow your instructions to run the Zedboard demo, after I trying `make hello` (the first time to synthesize the project), Vivdao complains about module 'zedbd' not found in …
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Which pins of ZedBoard are used for stdout of PULPino? It seems you've used EMIO connections of Zynq device for UART0 but I couldn't find location constraints within project files of pulpemu. Or did I…
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When i am trying to clone riscv-qemu & riscv-gnu-toolchain during the make -j my entire system get hanged . Also how to transfer spi_stim.txt file from PC to zedboard. Kindly share before ssh how to…
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Hello,
I ported the v3 implementation to a ZedBoard, using PMODs for UART and SD Card, and using memory through PS's (Processing System) HP (High Performance) AXI port. The idea is to setup a share…
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Hello,
I'm trying to add simple DMA device to the lowrisc (lowRISC 0-4 milestone release), I'm following the tutorial on the following link:
http://www.lowrisc.org/docs/internship-2016/device-tutori…
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I've successfully built master on Linux however I am having trouble building master on macOS X.
Here is my stamps dir:
```
ls stamps/
build-binutils-newlib
```
It's failing on the second s…
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Hello,
I want to make verilog DefaultFPGAConfig and I get the following error. Could anyone please tell me why I'm getting this error ?
Also, I want to make verilog for the zedboard, should I use…
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- [x] Are OCM drivers necessary?
- [x] Use demo to test http://henryomd.blogspot.co.uk/2014/10/using-zynq-ocm-linux-device-driver.html
[Technical Reference Manual](https://www.xilinx.com/suport/d…
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Hi dgschwend:
I'm trying to port zynqnet on a ZC706 board.
I've successfully generated HLS IP using codes under _HLS_CODE, and creat a BD project and generate a ZC706 bit in vivado. Next I create a …
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I run the command "make rocket" under fpga-zynq/zedboard.
When it run to the 40 line in the fpga-zynq/common/Makefrag :
make verilog MODEL=ZynqAdapter CONFIG=$(CONFIG); \
It will occur the error.…