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The techmapper for xc7 [https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc/xc7/techmap/cells_map.v](https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc/xc7/techmap/cells_map.v…
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https://console.cloud.google.com/storage/browser/_details/symbiflow-prjxray/artifacts/prod/foss-fpga-tools/prjxray/presubmit/database/artix7/1386/20200330-090521/database/diff.patch
```patch
diff --…
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I think I've encountered a bug that affects the pin mapping for the Basys3 board (part name xc7a35tcpg236-1). I've got a program that maps the 16 switches to a seven segment display but the behavior o…
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When I attempt to build the PicoSoC demo by running `TARGET="arty_100" make -C picosoc_demo`
it initially appears to build the example but then I get his error:
`Successfully finished Verilog fr…
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The [SymbiFlow project](https://symbiflow.github.io) is using [PicoSoC](https://github.com/cliffordwolf/picorv32/tree/master/picosoc). This is a "Cortex M0" style 32bit RISC-V processor + supporting i…
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It looks like the prjxray-db is inconsistent, for example in Artix7/Spartan7 there is
```
"LIOI3_SING_X0Y149": {
"bits": {
"CLB_IO_CLK": {
"alias": {
…
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Dear community,
First of all I want to say thank you for creating this project!
I am a total newcomer to everything related to RISC-V and I find it hard to get started.
So here is what I want…
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The solver from some of the INT pips seems to have changed from `050-pip-seed` to `056-pip-rem`. The bit patterns seem to be the same but the origin is changing.
**Is this expected?** If it is exp…
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VPR placer is not aware of whether placement of a block is legal in terms of its routability to other connected blocks (as the actual rr graph defines it). This poses an issues in architectures where …
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Moving my notes here from [openXC7-snap #4](https://github.com/openXC7/openXC7-snap/issues/4) as the following has nothing to do with the snap.
After losing to the 60GB Vivado monster on my WSL dri…