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Hello, I want to get rid of route_chan_width options to let Raptor find the minimum route channel width". Because inside Raptor, there is OpenFPGA which have 2 functions: one function is assigning a r…
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Similar to the issue #722 I am seeing that synthesis is failing
```
Project status:
[S] bitstream: bitstream -> /home/navaneeth/Projects/openmpw/CFU-Playground/soc/build/digilent_arty.proj_…
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When running the example, ERROR: TCL interpreter returned an error: couldn't read file _"/home/ankai/desktop/home/opt/f4pga/xc7/conda/envs/xc7/lib/python3.7/site-packages/f4pga /wrappers/tcl/xc7.f4pg…
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I am trying to synthesize a very simple circuit, targeting `xc7a50tcsg324-1`. I can take the same input and synthesize all the way to a bitfile with Vivado.
VPR fails with the following lengthy out…
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- \ and space char need to be removed before replication and re-inserted before composing
- primitive_databases is set up for edf, it would be nice for the database to be more generic
- to get th…
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The final installation command is very easy to mess up.
`for PKG in $F4PGA_PACKAGES; do
wget -qO- https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-d…
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For analysis of a7_100t's fasm,I use the command as this:
`**/root/Desktop/symbiflow/symbiflow-arch-defs/env/conda/envs/symbiflow_arch_def_base/bin/python3 -mfasm2bels --db_root /root/Desktop/symbif…
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I have installed Symbiflow following the instructions at https://f4pga-examples.readthedocs.io/en/latest/getting.html
With the conda environment active, I installed LiteX using the litex_setup.py s…
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Building digilent_arty.py with `--toolchain vivado` succeeds, but when built with `--toolchain f4pga` the build fails with the following error:
```
Found constant-zero generator '$abc$82080$auto$b…
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LiteX F4PGA issue
LiteX command:
```
!/content/litex-boards/litex_boards/targets/digilent_arty.py --toolchain=symbiflow --cpu-type=vexriscv --sys-clk-freq 80e6 --output-dir build/vexriscv/arty_35 -…