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iverilog simuation is too slow.
Could you introduce how to use verilator instead?
Thanks.
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When trying to `make compile` [RV64ACDFIMSU_Piccolo_iverilog](https://github.com/bluespec/Piccolo/tree/master/builds/RV64ACDFIMSU_Piccolo_iverilog) build of Piccolo:
```
/Piccolo/builds/RV64ACDFIMSU…
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Hi, I've installed the verilog linter using the package market directly from atom and had iverilog installed directly from the website. I'm not seeing any warnings/errors pop up when I edit my .vl fil…
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To be compatible with Icarus Verilog v10_2 (toolchain-iverilog v1.2.0)
Related to https://github.com/FPGAwars/icestudio/issues/209
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It seems that the iverilog invocation doesn't allow for SystemVerilog support:
https://github.com/google/xls/blob/c330e64365e56439ab9496159aa8664c6cd5eb6a/xls/simulation/simulators/iverilog_simulator…
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As not everybody has every package in their system installed on their search path, having an option to specify an explicit path for the iverilog executable would be useful.
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It seems that portions of Calyx's standard library written in SystemVerilog is not able to be simulated by Icarus.
```sh
[nix-shell:~/Repos/calyx] 11:12:38 $ iverilog -v
Icarus Verilog version 12…
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As we start to see more and more integration tests that require an IEEE simulator to run, it might make sense to add one to the CI. While proprietary simulators might be a pain to set up, we could sta…
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The code below sets bit 3 of all members of array a. I should print '8888' (tested with vcs).
However, I got this error running with "iverilog -g2012"
> mda.v:8: error: A reference to a wire or r…
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When working with a generated vendor module, it uses long attribute lines with line continuation marks, like the attached file [long_attribute_module.txt](https://github.com/steveicarus/iverilog/files…