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## My Environment
I wish to create a logic simulation environment while using ibex as a core. I have a question related on the structure of the core though.
1. Besides manual modific…
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I will use this issue to keep track of the status of my efforts to add cocotb support to VUnit and receive suggestions and feedback. I am new to VUnit (I haven't used it as a testbenching framework be…
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To raise-awareness and lower the barrier to testing Verible, should we push to deploy at edaplayground.com or consider our own playground? @mithro WDYT?
When we were brainstorming project ideas, h…
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Hi All,
I want to be able to declare something as below
```
module A (
input clk,
input rst_n,
output logic valid,
output logic ready,
…
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**Bug description**
Linting of a verilog file produces the error _Cannot read property 'logger' of undefined_.
As far as I can tell this isn't limited to modelsim, but I only have modelsim installed…
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The `boolean` data type is useful to declare variables/parameters which mean on/off.
Therefore, I'd like to introduce the `boolean` data type.
This is equivalent SV definition.
```systemverilog…
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I'm wondering if there is any ability to call a SystemVerilog/UVM Task/Function from Cocotb.
Instead of living in purely Cocotb, or purely UVM, is it possible from the python side to direct and con…
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https://wmchappy.cn/2020/12/26/sd/
快速记知识专用区 留言即可…..
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There are some parsers for HDL however all of them have some ridiculous weakness.
I would like to use [hdlConvertor](https://github.com/Nic30/hdlConvertor) because I know that the Python dependency…
Nic30 updated
5 years ago
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What would you like added/supported?
**typedef derived from type defined inside interface**
Can you attach an example that runs on other simulators? (Must be openly licensed, ideally in test_re…