-
I wrote a [RISC-V processor](https://github.com/jeras/rp32) in heavy SystemVerilog with a lot of:
* arrays, `struct`ures, `union`s, `typedef`s, `enumeration`s, custom type `parameter`s, ...
* assign…
jeras updated
2 years ago
-
- [ ] in the Bluespec simulator and
- [ ] via the Verilator backend build
-
When I did an exhaustive test on floating points, I noticed performance issue with fault generated testbench. The test vectors size is 0x500 * 0x500 = 0x190000 ~ 1 million data points. Here is the pro…
Kuree updated
3 years ago
-
I think I made a really poor assumption several months ago that I'm hoping someone with mixed signal design experience can clarify. If you have a digital top and you want to add in, say, an ADC black …
-
Right now, we are using a two-step setup for Synopsys VCS which according to http://www.vlsiip.com/vcs/ is limited to Verilog only. VCS(-MX) is capable of simulating VHDL too with a three-step process…
-
It can be useful to help the users simulate fault injections:
Implementation examples by Dolu1990 (via the Matrix channel)
```scala
def simBypass(that : UInt) = new Area{
val bypassEnabl…
-
There are multiple cases of simulators calling a registered **VPI** callback while cocotb is still inside a previous callback.
This causes `to_python()` to log an error and `exit(1)`.
- **icar…
-
SystemVerilog allows escaped identifiers in Section 5.6.1.
The rule is that they must start with an backslash and end with a white space. All printable ASCII characters are included in the name.
Y…
towoe updated
4 years ago
-
I'm trying to use configs for some test bench:
> config tb_cfg;
> // Define top
> design tb_lib.tb;
> /* rules begin */
> default liblist lib1 lib2;
> /* rules end */
> endconf…
-
Hello Serge,
You have done great work in this project. I really appreciate it. However, I am now stuck in the simulation step of kc705 testbench. I followed these steps to simulate it. I have gone to…