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I successfully booted Linux with FPU disabled. When I enable FPU, I get the following errors:
```
[ 0.156632] smp: Bringing up secondary CPUs ... …
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Here's an example of a test bench I have for something I'm working on. This is actually only a single test bench, stressing one part of the design; I have other tests that stress other things. It simp…
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I want to toggle the reset signal of a module in simulation, but I get an error that do not quite understand. Here is a simple example:
```python
from nmigen import *
from nmigen.back import pysi…
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Hi Lawrie and thanks for that great work!
As you mentioned:
> This implementation has been done from the specification, without access to any Raspberry Pi HDL. It is currently incomplete, but so…
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We are trying to use our 6T SRAM design instead of the BRAM for simulation. I understand that we would still need the BRAM to copy the image(vmem or elf) into the memory. My idea is to copy the …
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I will implement a version of `fpga-hdl2bit` based on edalize, to check similarities and differences. @mithro
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I'm using Vunit with verilog/systemverilog and xcelium
I have a strange issue. When in my setup I use multiple thread with the option:
python run.py --num-threads 5
Some tests are randomly fail…
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I have taken a quick look into supporting the Synopsys VCS simulator.
It looks like similar to Cadence's `cds.lib`, VCS needs a file `.synopsys_vss.setup` for the library name-to-path mapping. http://…
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A comment in Gitter ([November 30, 2019 10:35 AM](https://gitter.im/ghdl1/Lobby?at=5de237c5c3d6795b9ff8c77f)) lead to an interesting chat about Digital/Analog simulation with GHDL. There are two relat…
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How could we add time domain simulations to SAX?
similar to [photontorch](https://github.com/flaport/photontorch/)