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Hello, i try to generate the Verilog netlists and testbenches with the command "python3 openfpga_flow/scripts/run_fpga_task.py openfpga_shell/configuration_chain" you have given on the toturial.
But…
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This was triaged from openfpga, so please see the discussion over at https://github.com/azonenberg/openfpga/issues/11.
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openFPGA loader looks promising, but I see it is targeted to Linux with glibc only. Do you have any plans to port it to something else?
Current problems I see are:
- dependency on udev without if…
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I am trying to use your rtl at the integration exercise in order to feed it to our project OpenFPGA.
Even with the help of one of your students I am having issues getting the Verilog needed for our…
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Hi, can OpenFPGA build a bidir segment FPGA architecture?
I tried to change a undir segment FPGA, which was `k6_N10_sram_chain_HC_template.xml`, to a bidir segment by modifying the content of the ``…
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I try to use python3 to run openfpga flow, but there are some error which I can't fix:
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lab601@lab601-VirtualBox:~/Desktop/OpenFPGA-master/openfpga_flow/scripts/test$ py…
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I try to build OpenFPGA, and cmake has a error result, this is content of the CMakeError.log file:
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Performing C++ SOURCE FILE Test CXX_COMPI…
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For some reason, I want to describe a custom switch block connection for my FPGA architecture, but not use the way which VTR 8.0 provide to choose custom SB type.
I try to modify `rr_graph_sbox.cp…
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We need to make sure the content of the .route file is consistent with the routing while the tillable option is activated.
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Hi, I came across PRGA topic while searching for open source FPGA and EDA tools, looks really amazing; I am very new to these open-source tools and Python. While building **k4_N2_8x8** as per **docs/s…