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Performing a AXI4 to WB conversion using the recommended components (per the repo's README.md)
Issued a single write, which successfully propagated to the WB target. The axlite2wbsp component succ…
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Each AXI slave should have a separate control parameter in scala, currently multiple AXI slaves all get the same one
Example:
val axi4_slv0Node = AXI4SlaveNode(
Seq(
AXI4SlavePortPa…
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Hi Pavel,
Hope your having a great day.
I was trying to impliment sine and cosine both signals on two different dacs.
for ex: from dds (29:16 sin to dac 1 so out1 and 13:0 cosine to dac 2)
so …
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Instead of running a whole project of rocket-chip, I wonder if it is possible to just emit a minimal AXI4 Module for `PWM`, which is much easier to evaluate by Xilinx ZYNQ FPGAs or simply used as DUT …
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Simply from reading the code at https://github.com/bluespec/Piccolo/blob/master/src_Testbench/Fabrics/AXI4/AXI4_Deburster.bsv#L174 (understand "I have not tested what I am about to claim in any way"),…
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If transmitting larger packets over fifo in non-blocking mode it comes to over-read error after certain data amount is transmitted.
The proposed solution is to check occupancy and rxLength so that al…
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Is it possible to use a Vivado IP core within a FireSim target design?
After reading the section about [Restrictions on Target RTL](https://docs.fires.im/en/latest/Advanced-Usage/Generating-Differe…
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https://github.com/bespoke-silicon-group/bsg_f1/blob/3be88f28d1a3e84e8f133a226a9a73fbccd53ee6/cl_manycore/hardware/cl_manycore.sv#L174-L216
For example:
```
logic [2*6-1:0] m_axi4_concat_awid;
`…
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Create documentation for the IP-package, either as Wiki page or as ReadMe. While the source code is commented and it should be clear what each register of the AXI4-Lite interface does, it may be bette…
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https://github.com/bespoke-silicon-group/bsg_f1/blob/be0d7b91ebc6028e9e5ba0f7f8b653f4e9ab486d/hdl/axil_to_mcl.v#L1
A description of what this is. Why is there a crossbar? Is it a single link or mul…