bluespec Piccolo issues

bluespec / Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Apache License 2.0

311 stars 49 forks source link

issues

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relocation truncated error when compiling `elf_to_hex.c` file to create the Mem Hex files

#44 jrmejiaa opened 1 year ago
1
The Architecture Documentation

#43 fangwenji opened 2 years ago
0
Cache replacement policy / Shrinking Size

#42 LeonardooAlves closed 2 years ago
0
How to generate VCD files for simulations?

#41 LeonardooAlves closed 2 years ago
1
Does Piccolo run FreeRTOS?

#40 LeonardooAlves opened 3 years ago
6
PLIC: Allow multiple interrupts to be claimed but not completed

#39 jrtc27 closed 3 years ago
0
Building and Running from the Verilog Sources, out of the box results in Error

#38 nishanthsmurthy24 closed 3 years ago
1
Can the project be taken to Google summer of code 2021 as organization

#37 pawan-nirpal-031 opened 3 years ago
1
porting dhrystone on Vegaboard

#36 sharayup12 opened 4 years ago
0
Small build cleanups

#35 davidchisnall closed 3 years ago
0
Toolchain support for custom opcodes

#34 nirajnsharma opened 4 years ago
0
Reference TCA Design

#33 nirajnsharma opened 4 years ago
0
CPU modification for custom opcodes

#32 nirajnsharma opened 4 years ago
0
Running Dhrystone or CoreMarks benchmarks

#31 kammoh opened 4 years ago
0
AXI Fabric bugs

#30 ZipCPU opened 4 years ago
1
Make SRET illegal when S-mode not supported

#29 PeterRugg closed 4 years ago
0
Can't run simulator, missing symbol _Z27dollar_test_dollar_plusargsP9tSimStatePKcPKSs

#28 hlandau closed 4 years ago
2
CPU_Decode_C: C.FLWSP/C.FLDSP are legal when rd == 0

#27 jrtc27 closed 4 years ago
0
fcvt.w.d rounds incorrectly in rmm mode

#26 michael-roe opened 4 years ago
0
fcvt.wu.d does not round up denormalized values

#25 michael-roe opened 4 years ago
0
nmsub.s of all (positive) zeros

#24 michael-roe opened 4 years ago
0
fcvt.wu.s of negative zero

#23 michael-roe opened 4 years ago
0
Added check for NaN on output of FP compute pipelines

#22 nirajnsharma closed 5 years ago
0
CSR_RegFile_MSU.bsv: Legalise PC on SRET as with MRET

#21 jrtc27 closed 5 years ago
0
mkBuild_Dir.py: Fix ISA_M condition copy paste error

#20 jrtc27 closed 5 years ago
0
No C extension causes Piccolo compile failure

#19 jsburke closed 5 years ago
3
SC to 4-byte aligned but not 8-byte aligned address will always report success

#18 PeterRugg closed 5 years ago
2
AXI4 unify

#17 gameboo opened 5 years ago
0
Suspicion of bug in the deburster

#16 gameboo closed 5 years ago
1
Fix reading and writing to mtimeh/mtimecmph on 64b Fabrics

#15 heshamelmatary opened 5 years ago
0
Add constraints to Xilinx IP project for the internal JTAG clock

#14 dhand-galois closed 5 years ago
0
Update the Xilinx IP packaging for the SSITH P1 to include the WID ports

#13 quark17 closed 5 years ago
0
verbosity of MMU_Cache is always 0

#12 TarekIbnZiad closed 5 years ago
1
Mixed code indentation

#11 GiuseppeDiGuglielmo closed 5 years ago
2
FBox bug fixes.

#10 nirajnsharma closed 5 years ago
0
Illegal instruction not handled properly

#9 acw1251 closed 5 years ago
1
FBox Integration

#8 nirajnsharma closed 5 years ago
0
Fix the SoC reset so that it can be called more than once

#7 quark17 closed 6 years ago
0
Fix a typo in the computation of MLEN

#6 quark17 closed 6 years ago
0
In the trace encoder, fix the generation of the group for memory writes.

#5 quark17 closed 6 years ago
0
Fixes to compile without ISA_PRIV_S and to interoperate with other BRVF_Core versions

#4 quark17 closed 6 years ago
0
Fixes to get code to compile with different macro definitions than usual

#3 quark17 closed 6 years ago
0
dhrystone test

#2 chlizheng closed 5 years ago
0
when run DC, BRAM.v has Error

#1 chlizheng closed 5 years ago
0