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The test generation flow appears broken when I try to customize the default target rv64gc with PMP support for SV39 mode on Mentor or Cadence simulators?
I've pulled in upstreams upto `d74484b -…
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This plugin works great until I tried to set it up for linting a testbench. I modified my arguments to compile the full testbench because per-file compiling doesn't work when there are class-based dep…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…
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### Version
Yosys 0.31+49 (git sha1 e0ba07aed, x86_64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os)
### On which OS did this happen?
macOS
### Reproduction Steps
Try to `read_verilog -sv` on …
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Hi ,
Can you tell me where can i find information
about the usb registers structure you're using here?
Thanks,
Sally
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So I have the following magma code:
```python
import magma as m
class Foo(m.Circuit):
io = m.IO(I=m.In(m.Bits[8]), O=m.Out(m.Bits[8]))
tmp = io.I + 42
io.O @= tmp
m.comp…
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Using Git version of Verilator.
I will try to describe various errors I encountered, but will not provide code to reproduce each one, since they are probably related. At the end are instructions to…
jeras updated
3 years ago
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### Describe the bug
When using the single comment style of language injection, as introduced in #6418, the nix code between two injections has the incorrect commentstring
```nix
foo = # lua
"…
alxdb updated
1 month ago
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### Tool name
Verilator
### Tool license
None
### Add or update?
- [ ] Add
- [X] Update
### Desired version
5.029
### Approximate size
_No response_
### Brief description of tool
Allows tra…
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Hello, I am attempting to write a testbench in verilog for the Arty A7 in order to send a simple message from the board to a mobile device, but am having trouble translating how the ethernet frame var…