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pulp-platform
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cheshire
A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
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AXI version `v0.39.4` breaks Linux boot
#157
alex96295
opened
1 day ago
1
changing AXI datawidth is not available.
#156
SeongRyong0726
opened
2 days ago
1
usb regs
#155
sallyakj
opened
1 week ago
0
Add VCU118 support to ara-pulpv1-os
#154
mrbilandi
opened
1 week ago
0
Add VCU118 Support
#153
mrbilandi
opened
1 week ago
0
CHANGELOG.md: Release v0.1.0
#152
paulsc96
closed
1 week ago
0
hw: Default on VGA with RGB565
#151
paulsc96
closed
1 week ago
0
decrease bootrom SPI frequency
#150
mrbilandi
closed
1 week ago
0
Correctly initialize stack pointer in memisl linker script
#149
sermazz
closed
1 week ago
0
Lleone/memisland
#148
Lore0599
closed
2 weeks ago
0
hw: Add missing cast in ambiguous default expression
#147
phsauter
closed
1 week ago
0
make: Formalize phonies and document tool path vars
#146
paulsc96
closed
1 month ago
0
Enable ACE cut
#145
ricted98
closed
1 month ago
0
Add Culsans features on top of Astral branch
#144
ricted98
closed
1 month ago
0
USB host interface
#143
sallyakj
closed
1 month ago
1
Peripherals Clock Gating
#142
Lore0599
closed
1 month ago
1
target/sim: Correctly handle empty UART lines
#141
niwis
closed
1 month ago
0
Resolve conflicts between `astral-culsans-complete` and `astral-v0`
#140
ricted98
closed
1 month ago
0
USB errors with Linux
#139
krabo0om
closed
1 month ago
2
Interrupt handler
#138
SeongRyong0726
closed
1 month ago
0
Add ECC axi_llc (single error handling) to astral-v0 cheshire
#137
Aquaticfuller
closed
2 months ago
0
target/sim: Add DRAMSys main memory option
#136
niwis
closed
1 month ago
0
target/xilinx: Remove quotes on `tclargs`
#135
paulsc96
closed
2 months ago
0
Vivado's -tclargs does not use quotes
#134
krabo0om
closed
2 months ago
5
doc: Some cleanup and improvements
#133
paulsc96
closed
3 months ago
0
hw: Fix widths of `doub_bt` parameter literals
#132
paulsc96
closed
3 months ago
0
ci: Add Tcl linting, update `pulp-actions`
#131
paulsc96
closed
3 months ago
0
Indication on how to modify FPGA tools version
#130
pcotret
closed
1 month ago
0
Integrate Culsans on top of Astral modifications.
#129
yvantor
opened
3 months ago
0
Add ECC axi_llc (uncorrectable error handling) to astral-v0 cheshire
#128
Aquaticfuller
opened
4 months ago
0
target/fpga: Add Hyperram
#127
niwis
opened
4 months ago
0
IOMMU Integration
#126
maicolciani
closed
3 months ago
1
Initial ecc llc integration
#125
Aquaticfuller
opened
5 months ago
0
sw: Collection of build environment issues
#124
paulsc96
opened
5 months ago
0
target/xilinx: Fix typo in type parameter
#123
niwis
closed
5 months ago
0
Integrate DMa v0.6
#122
yvantor
opened
5 months ago
0
idma V0.6.0 integration
#121
chaoqun-liang
closed
5 months ago
0
Cl/idma wrapper
#120
chaoqun-liang
closed
5 months ago
0
treewide: Connect LLC performance counters to cheshire regs
#119
alex96295
opened
5 months ago
0
Bender: Bump AXI-REALM
#118
alex96295
opened
6 months ago
0
Generate FAT partition containing uImage for new loading mechanism
#117
TheSmolBoi
closed
1 month ago
1
make: Ensure correct path to `xilinx.mk`
#116
phsauter
closed
5 months ago
0
Cl/eth astral
#115
chaoqun-liang
opened
6 months ago
0
hw: Disable CVA6 `FP8ALT` support
#114
lucabertaccini
closed
7 months ago
0
hw: Update `axi_vga` to fix performance issue
#113
thommythomaso
closed
7 months ago
0
Ara integration in Cheshire
#112
mp-17
opened
7 months ago
10
Integrate Ara in Cheshire
#111
mp-17
closed
7 months ago
0
Astral new
#110
yvantor
opened
7 months ago
0
Integrate HMR unit for CVA6 redundant grouping
#109
yvantor
opened
7 months ago
0
Enabling `BusErr` breaks SD card boot on FPGA
#108
paulsc96
closed
5 months ago
1
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