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Hi,
I struggled with this strange issue for a couple of days and finally found out that,
for some weird reason, configuration failed (DONE pin on the FPGA not coming high)
when I tried to load a L…
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I am trying to build FemtoRV petitbateu but it fails to build two different ways for two different toolchains.
When I build with yosys+nextpnr using command: `python3 -m litex_boards.targets.digile…
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VPR is routing some designs on artix200t through unknown GTP PIPs.
In those designs, the GTP tiles carry the horizontal clocks to the BUFHCE primitives. Since the interconnect points are "real" and …
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We should be able to add support for [RPC DRAM](https://etronamerica.com/products/rpc-dram/) in LiteDRAM.
RPC DRAM reduces DDR3 pin count by removing all the command/address lines, data mask and CK…
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HI
I'd like if there is some option to flash given file unmodified,
directly to flash chip, starting from some offset.
To make code simpler, It's acceptable if offset
has to be multiple of 4K …
emard updated
2 years ago
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This is probably more of a "support" question. :S
# Background
I am trying to learn how I can stream data from sdram to something else, probably running at a lower clock rate.
Right now I am lo…
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Hi there,
Since the `prjxray-db` of Spartan-7 was generated last month, I've been trying to add support for Spartan-7 to `arch-defs`. Following @acomodi's [instructions](https://github.com/SymbiFlo…
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With the clock propagation enhancements done in https://github.com/SymbiFlow/yosys-symbiflow-plugins/pull/54, the resulting SDC does not take into account the output clock from BUFGs connected to the …
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In push https://github.com/SymbiFlow/prjxray-db/commit/a11a64c2fd2627dea6fe596ab24775519b0e5012 it seems a bunch of stuff disappeared.
I believe the PLL changes were expected but there seems to ha…
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The last step of the installation is to install a set of tar files like this:
```
mkdir -p $INSTALL_DIR/xc7/install
wget -qO- https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-…