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This will translate the crank and cam signals into engine and cam angle.
the aim is to achieve OEM levels of accuracy up to 20k crank rpm.
Gathering details on bosch gtm, nxp etpu and ti hwag wi…
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*Moved from https://github.com/trabucayre/openFPGALoader/pull/102#issuecomment-895953900.*
@trabucayre, I would like to propose joining forces with [hdl/constraints](https://github.com/hdl/constrai…
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Please add a way to prove my nic-hdl in the RIPE database.
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got error from yosys when generating the gl of UART with wrapper
files in synthesis:
- /hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
- /hdl/rtl/bus_wrappers/EF_UART_APB.pp.v
- /hdl/rtl/bus_wrappers/E…
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I am trying to enable the HFP PTS test case in my side. In some cases. When one wid is triggered, one BTP cmd is sent to IUT, then wait the response of the BTP cmd in the wid function. When waiting fo…
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I have been using cocotb for a while and decided to switch to the Python runner approach instead of using a Makefile.
The problem that I found is that, when I use Xcelium as a simulator and open th…
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**Describe the bug**
I have code that generates the following SPI Engine instructions:
```
[ 45.198984] ad4695 spi0.0: CMD: 0x2103 CPHA=1, CPOL=1
[ 45.199002] ad4695 spi0.0: CMD: 0x10fe …
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Hello, nice job! Library is awesome! What about curtain control? Are you going to support other types of devices from HDL?
sou1t updated
2 weeks ago
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Hi,
First of all, thank you for this generator!
I think it would be really nice to have the generation process generate the register address mapping in VHDL as constants in a package, and not as ma…
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On simulation `ConcatSignal` requires more than one argument [1] but it gives a error when converting to vhdl/verilog.
> Not supported: extra positional arguments
## System information
…