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**Describe the bug**
Hello, I found that when importing my custom sense amplifier into OpenRAM, it overlaps two sense amplifiers together. It defines the width of my custom sense amplifier as the wid…
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### Description
Hi all,
I create this issues due to i'm working on a project with OpenRAM, i create a module that combine two SRAM macros to work as one, the problem comes when i update OpenLane l…
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I am writing a [system bus protocol specification](https://github.com/jeras/TCB) and I have spent more time than I expected thinking about explicit bi-endian and unaligned access support. I would like…
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I put PNGdec in clockwise\components and add a CMakeLists.txt file as below
```cmake
cmake_minimum_required(VERSION 3.15)
if(ESP_PLATFORM)
# Build ArduinoJson as an ESP-IDF component
idf_co…
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The simulation with the `riscV (VexRISC) ` cpu is way slower than `swift2`. `Swift2 `is faster more than 4 times. This may be because `riscV (VexRISC) `cpu doesn't have cache memory and it's using `SP…
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It would be awesome to see how this CPU would work in ASIC form and Google is offering free tape outs to open source silicon projects on SkyWater's 130nm and GlobalFoundries 180nm MCU process technolo…
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### Description
I have successfully generated GDSII file with open lane for picorv32 with configuration using docker container.
However when I try to get GDSII for Rocket chip with Tiny configuratio…
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**Is your feature request related to a problem? Please describe.**
A clear and concise description of what the problem is. Ex. I'm always frustrated when [...]
**Describe the solution you'd like**…
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**Describe the bug**
Note that I'm not an expert in this, but my understanding is that we need a liberty file to do static timing analysis of a ROM when incorporating it into a larger design as a pre…
galv updated
2 months ago
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I request that the following data is removed from The Stack:
- TrechNex/mastodome-legacy
- TrechNex/gimp-macos-build
_Note_: If you don't want all resources to be included just remove the el…