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Hi, I am currently trying to improve upon the base statistics generated when running the Coremark example.
I am running with the following command
` make -f $RV_ROOT/tools/Makefile $@ target=default…
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**Is your feature request related to a problem? Please describe.**
To be more user friendly, PSL assertions could be added to waveform dump (GHW only since FST and VCD).
**Describe the solution yo…
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Hello
I'm interested in this project, since am working on a commercial version of a FIRRTL Simulator implemented in Scala for large SoC designs. Our goal is to support Rocket and Boom simulations …
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could someone help me to solve the error ? thanks first.
I don't like sbt very much, and try to transform *.scala to *.v as below:
1. download 'chisel3_2.12-3.1.6.jar' from https://mvnrepository…
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### Description
This is a bucket-issue for improving Questa support in OpenTitan.
> I want to use this issue to drive support forwards by gathering user feedback into a working branch of fixes, …
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**Issue by [Fatsie](https://github.com/Fatsie)**
_Saturday Nov 16, 2019 at 13:21 GMT_
_Originally opened as https://github.com/m-labs/nmigen/pull/270_
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I am using nmigen for generating RTL to b…
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Tried this in release 3.7 on Ultimate II, 3.10a on Ultimate 64 Elite and 3.10e on Ultimate II+L:
Using Commodore MPS, Epson FX-80/JX-80, IBM Graphics or IBM Proprinter emulations, once a printed li…
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Right now, the scope of formal is the following, copied directly from IRC:
>(11:56:43 AM) whitequark: the entire scope of formal verification in nmigen at the moment is "it can generate verilog or …
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needed for definition of done. creating an issue for tracking