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There are some parsers for HDL however all of them have some ridiculous weakness.
I would like to use [hdlConvertor](https://github.com/Nic30/hdlConvertor) because I know that the Python dependency…
Nic30 updated
5 years ago
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Not sure if this is a great title, so I can change it if necessary. I have been having an issue recently, where I have _huge_ delays when my editor (Neovim) goes to complete something. I boiled it dow…
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**Description**
I am trying to compile ```.vhd``` file with ```ghdl``` using ```ghdl -a``` command at terminal on MacOS 14.6. I encountered the error ```ghdl:error: installation problem: ghdl1-llvm n…
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Is the TanhLayer.vhdl's logic correct?. it just bit slices the SUM_WIDTH long bit array to BITWIDTH wide. it won't even consider the sign bit. Just take the least significant BITWIDTH bits.
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A view to navigate through the design (hierarchy Source files) would be a very helpful feature of this extension.
something like the (a bit imprecise) vhdl-hierarchy extension...
https://marketplac…
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Just like the VHDL or Verilog Generation, does SpinalHDL generate SystemVerilog codes and needs some basic info about using the verification environment in SpinalHDL?
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Hi
I've been experimenting some more with Digital exports to Quartus for compilation/synthesis into a CPLD. This time I am exporting my design to VHDL and importing into Quartus. My project has two…
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Error: ../testcase.e.vhdl(8): (vcom-1598) Library "osvvm" not found.
Error: ../testcase.e.vhdl(9): (vcom-1474) Selected name prefix "osvvm" in context reference is not a library name.
Error: ../t…
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```
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity blink is
port (
clk : in std_logic;
inp : in std_logic_vector(63 downto 0);
…
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The line #include won't compile as the file is missing.