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Hi~
SpinalHDL language itself has good generalization and maintainability,
But the quality of the verilog code it generates is not high, the maintainability is poor, and it is difficult to meet the…
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Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will …
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First of all, congratulation on the project.
It would be great for `nvc` to also act as an LSP server.
Any plan for the future?
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The following simple test with `clashi` segfaults on macos 12:
```
% cat test.hs
{-# LANGUAGE DataKinds, NoImplicitPrelude #-}
import Clash.Prelude
topEntity :: Signal System Bit -> Signal Syste…
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I have been able to integrate VCSMX into the VUNIT infrastructure.
I updated
o sim_if/vcsmx.py
o sim_if/factory.py
o vcsmx_setup_file.py
- I have also added some print diagnostics to
o suites…
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We have some places in our code where we hackishly/partially parse (parts of) SystemVerilog. It would be nice to choose an existing parser and integrate it properly into the codebase.
Currently we …
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GHDL's documentation has evolved a lot since the last years. It started with compile instructions and a tiny example and how we have a the content of a book. With #1580 and similar PRs we added Python…
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Not sure where else to put this, but I was actually interested in this exact same concept, and there isn't really anything on the 'net about this. Do you have any interest in working on this project?
…
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[This issue has been opened to continue work on an unfinished topic from Ada 2022. This was done in response to the ARG Resolution of November 2022. This is the last topic that will be "promoted" this…
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Hi, I think I've hit a bug similar to #3078 , but a bit more difficult to trigger.
I've got a mixed-language design with both verilog and VHDL modules. For this particular case the path looks like th…