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A number of fuzzers (and associated minitests) work on Vivado 2017.2 but are broken on Vivado 2017.3. A quick analysis shows its related to MUXF8.
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Hi,
I had similar problem with JTAG interface based on ESP8266 in lua.
The solution is to call tmr.wdclr() periodically in the loop, in which you perform transfers.
HTH & Regards,
Wojtek
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Dear Sirs
I apologize for me English
It is quite difficult to describe this issue: a block instance create the following message:
******************** GHDL Bug occurred **********************…
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I will implement a version of `fpga-hdl2bit` based on edalize, to check similarities and differences. @mithro
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The simplest possible block RAM, one that is initialized to all zeroes:
```
import Clash.Prelude
type Addr = Unsigned 13
type Value = Unsigned 8
topEntity
:: Clock System Source
-…
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I attempted to convert this project to Verilog so I could use it in Xilinx ISE.
I used a utility called sv2v (https://github.com/zachjs/sv2v).
I had to change 3 wires to reg after conversion and the…
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Hello,
I am new to cpld programming.
Maybe you could help me.
I use vivado from Xilink.
I created a new project and added all the verilog files provided on this page. When generating the bit…
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Hello,
I've successfully synthetized the whole VHDL code to fit a spartan-6 and simulated it with Xilinx tools.
Now I would like to put my own sketch in the softcore program memory.
But to start wi…
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Hello!
I used "OpenRISC SoC Practical Session Instructions" to get my very first OpenRISC experience.
All steps were OK, but this one fails:
`fusesoc sim mor1kx-generic --elf-load hello.elf`
I g…
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Verilator does not complain when a _reg_ type is connected to output port of module instance.
See the following example:
```
submod.v:
module submod (
input wire CLK,
input wire RESE…