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Hello,
I am trying to obtain the VCD file from an execution of a the hello example code in the Simple Runtime using the Ibex (formely zero-riscy) core.
I run my code using `make run vsim/script=…
Merok updated
3 years ago
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## Issue
It recently came up in the RISC-V meeting that the bitfield syntax is limited when we want bitfields with fields that can vary in width depending on XLEN, or the virtual memory translation…
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Currently the verilog for commonlib.MuxN is generated like the following:
```
module commonlib_muxn__N2__width9 (
input [8:0] in_data [1:0],
input [0:0] in_sel,
output [8:0] out
);…
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Symbols get added to the symbol cache in `gatherFiles` ([specifically this `TypeSwitch`](https://github.com/llvm/circt/blob/d2e29b53634ca64d66c1d32f57210f4ec40d0fe5/lib/Conversion/ExportVerilog/Export…
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I would like to compile my SV code with yosys+UHDM, I followed the instructions from here:
https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/
except I…
jeras updated
2 years ago
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Using two different types in two different generate branches for the same signal results in the following error:
```
sv2v: field 'field1' not found in struct packed {
logic field2;
}, in expres…
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There should be a file for each language that covers every edge case. The file should contain every variant comments and quotes, as well as a comment at the top of the file containing the **manually**…
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I just found https://github.com/dalance/svlint and would be interested how it copes with the ibex code base.
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I am currently working on enabling xfuzz support for NutShell(as DUT) and have made the following modifications:
I added ccover support in build.sc:
import mill._, scalalib._
import coursier.mave…