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unning with RISCV=/root/chipyard/esp-tools-install
mkdir -p /root/chipyard/sims/vcs/generated-src/chipyard.TestHarness.TramSoCConfig
cd /root/chipyard && java -Xmx8G -Xss8M -XX:MaxPermSize=256M -Dja…
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Let's run the pandoc formatter:
`$ pandoc --wrap=preserve spec.md -o spec.md`
Additionally, let's make sure we get this integrated into CI.
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@jerryz123 @seldridge firtool fails to generate Verilog from attached .fir file. It was generated using latest Chipyard and running `cd vlsi && make buildfile tutorial=sky130-openroad CONFIG=MegaBoomC…
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Simple class with input driven by an integer:
```firrtl
FIRRTL version 3.2.0
circuit InputProp:
class Test :
input in : Integer
module InputProp:
object o of Test
propassig…
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Assertion failure in `circt-opt -pass-pipeline="builtin.module(lower-firrtl-to-hw)"`
```mlir
firrtl.circuit "foo" {
firrtl.module @foo() {
%c = firrtl.constant 0 : !firrtl.uint
%145…
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I tried to use another config other than DefaultConfig when making, but was warned the following:
```shell
cd vsim
make CONFIG=DefaultRV32Config
```
```
mkdir -p /home/hujiyong/RISCV/rocket-chi…
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**Type of issue**: Bug Report
**Please provide the steps to reproduce the problem:**
I opened a draft PR: https://github.com/chipsalliance/chisel/pull/3635. This adds checking for Property t…
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I am trying to run the Tiny Rocket Core in Xilinx zcu102 FPGA. I tried with Default Rocket Core and it is working fine.
Is this Tiny Core required additional changes in the Scala Files.
**I am u…
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### Describe the bug
The rust code below fails to generate a full CST when calling `:Inspect`:
```rust
fn main() {
println!("{}", ok);
println!("ok");
}
```
Instead, the tree below…
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Currently, FIRRTL external modules with either input or output property ports error during `LowerClasses`.
I haven't thought through exactly how this should work in terms of lowering. At a high lev…