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*Edit by @dmerejkowsky, so that the task list appears in the issue*:
Guides to write:
* [x] Creating a basic manifest repo, using `init` and `sync`
* [x] Editing `.tsrc/manifest.yml`
* [x] Usin…
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I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog.
Vivado supports SV but not Spartan 6 family :-(
I tried to translate this code to Verilog but packe…
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Currently, metadata pertaining to grammars and case-by-case exceptions are handled in four different places:
* [`.gitmodules`](https://github.com/github/linguist/blob/b7f579597050aaf7ac19c6c6ec5042…
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In array assignment patterns, verilator does not apply the default keyword recursively to subarrays.
For example, in this case:
```verilog
module dut;
int a[4][4] = '{default: 0};
endmodule
…
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### Version
Yosys 0.38 (git sha1 543faed9c8c, gcc 13.2.0-13 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
E.G.
yosys -p "read_verilog -sv ../../icebreaker2_nosv.v; syn…
spth updated
7 months ago
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### Version
Yosys 0.28+6 (git sha1 cee3cb31b, clang 10.0.0-4ubuntu1 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
Verilog file:
```verilog
module top (res, offset);
…
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```bluespec
import TriState::*;
interface T;
interface Inout#(bit) v;
endinterface
(* synthesize *)
module t(T);
let t
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We want a structured way to write unit tests for the sim.v files (and a way to run them).
We want the unit tests to be compatible with at a minimum;
* Yosys
* Verilator
* Icarus Verilog
Bu…
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how can we find code coverage?
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**Is your feature request related to a problem? Please describe.**
It's not uncommon for registers (especially MMIO config) to contain bits/bytes pulled from other registers/regions of memory. These …