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Hi,
when trying to integrate the SHA3 rocc into the latest rocket chip (rev 25e1412) I get the following error during compilation o the emulator
~/git-rocket-chip/emulator$ make CONFIG=Sha3CPPConfig…
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When I try to modify the `RC_CLK_MULT` and `RC_CLK_DIVIDE` variables in the file `src/verilog/clocking.vh` to increase the processor frequency, Vivado seems to ignore the `RC_CLK_DIVIDE` value and use…
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Hi,
I'm getting an error using the cmd-line below (see (1) below)
cd rocket-chip/vsim
make verilog CONFIG=SmallConfig
Is there something wrong in my cmd-line setting and what's the correction?
I di…
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I can successfully build riscv tool chain in isolation; however, if i try to build riscv tool chain with the instruction given in your docs, meaning:
cd $ROCKETCHIP/riscv-tools
git submodule update -…
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Hello,
I was wondering if it is possible to run bare-metal applications with rocketchip? I wanted to simply flash a program written in C without using bootloader and flashing linux image to ROM. If …
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I have been told that Vec's of size 0 is not supported. I would like for them to be supported.
I have a pipeline of a parameterized size `num_stages`:
``` scala
val r_valids = Reg(init = Vec.fill(n…
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Hi,
Which configuration file allows one to change ICACHE, DCACHE sizes and number of RocketChip cores?
Thanks,
David
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Hi,
I was able to generate the verilog for the rocketchip.
However, I saw there is an AXI like interface "io_mem_*".
Is there systemverilog code that takes the AXI -like master signals from Top
and …
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Got this FIRRTL error in Travis.
https://travis-ci.org/ucb-bar/rocket-chip/jobs/120801507#L1274
What does this mean, exactly. Is it an internal FIRRTL issue?
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Hi,
I'm a little confused by the various implementations of RISCV :
RocketChip (original SOC from UCB with HTIF)
zscale (RISCV 3 pipeline with no cache)
but where to find the untethered lowRISC by …