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### Description
This test (which runs in `rma`, `dev`, and `test_unlocked1`) has been failing on FPGAs since commit b2239fc38e0725f17b1155d7e48ec6403facf7f6.
That commit is almost certainly not …
jwnrt updated
4 months ago
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Is there any undocumented flow for embedded FW development using a MicroBlaze inside the CL, with the AWS-FPGA HDK?
In my on-premise environment, using u200 card, and following the instructions fro…
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there are several ftdi based jtag probes, like flyswatter2, bus blaster, xds100 and others
even all use same/similar chip, mpsse settings are different.
in pyftdi it is hardcoded. for example openoc…
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Hello!
There is a Pluto+ Rev2 on hand. When programming any firmware (official AD or pluto+ firmware) via JTAG with the DLC10 programmer in Vivado 2020.2 the following errors occur: ERROR: [Labtools…
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So I'm stuck when trying to load big(relatively) firmware/program to the ibex-demo-system. After several trial, I find that if the program file is smaller than 9408 bytes as shown below (9404B), it wi…
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### Board
ESP32-S3-DevKitC-1-N-32R8V
### Device Description
ESP32-S3-DevKitC with only USB serial cable attached.
### Hardware Configuration
n/a other than onboard RGB used in sketch.
…
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The JTAG is accessible on expose IOs connector. Will be more easy if it is a separated connector.
Connector 2x5 din will be added with JTAGice MkII layout:
 specifies the following functions for pins `A18` and `A19`
- A19: GPIOA_19 UART1_RX JTAG_TCK PWM_7
- A18: GPIOA_18 UART1_TX…
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I like where this is going, but it would be really nice to fit the uart in the 8 pin option.
I would suggest this as an enhanced pinout for jtag/uart options:
1 GND
2 SWDIO/TMS
3 SWCLK/TCK
4 nRE…