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Develop tooling to help with non-trivial flow graphs. Somewhat like the old `migen.flow` scheme.
## Features
* pipelining the components to get maximum throughput and minimum delay
* handle `st…
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I'd like to get a list together of all the current documentation, guides and example code to learn the basics of FPGAs and how they compare to developing on something like an Arduino.
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Using the target for the tang nano 9k with no modifications.
made with
```bash
litex_boards.targets.sipeed_tang_nano_9k --build --flash --cpu-type=vexriscv --cpu-variant lite
```
```bash
…
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Hi again,
I've been playing around with the migen acm example on the fomu for a bit now.
While testing the connection and it's limits I've come across problems I can't seem to solve.
Probably it'…
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More technical details at [HDMI2USB-misoc-firmware#133: Allow HDMI2USB devices to act as HDMI extenders via the Gigabit Ethernet port](https://github.com/timvideos/HDMI2USB-misoc-firmware/issues/133)
…
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Hi,
Is there any way to generate the Liteeth Core Verilog independent of specific vendors?
When generating the Verilog with the examples (`liteeth_gen wishbone_mii.yml`) the generated Verilog uses…
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```
I am getting this error when launching in tomcat. Searching on the web suggests
that library is missing but I tried adding it in various places. We had this
issue in MiGen and had to resolve to …
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Hello everyone.
I have been trying to build "firmware" for an FPGA and I'm receiving such error
```
Traceback (most recent call last):
File "build.py", line 28, in
top = OV3(plat)
F…
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On Microwatt (a 64 bit CPU) we have to narrow/widen the 32 bit litesdcard DMA wishbone bus:
https://github.com/antonblanchard/microwatt/blob/84473eda1b54a03794b2f3d13748f42b52ead34e/soc.vhdl#L247
…
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Hello,
I was working on similar project.
My problem was that Vivado has too slow start and it was much more effective if it was running as a backend server and the client was sending the jobs fo…
Nic30 updated
5 years ago