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Currently, the code basically relies on Cairo for rendering (pixmap or vector format). I would like to be able to generate output suitable for use with OpenSceneGraph and similar 3D rendering librari…
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Currently VPR can only lock down the placement of I/Os (in the pads file), and there isn't a direct way to control the clusterer with constraints.
1. We should have a method to lock any primitive…
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Feedback- or profile-directed optimizations (FDO) generally work by compiling a program once, profiling it at runtime, and then using the profiled information to optimize the program for the particu…
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Hi!
I am new to parsing and trying to learn by writing a spice netlist parser. In the first line of a spice netlist, there is an optional title string that gives the title to the circuit. How would…
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How could we enable [SAX](https://flaport.github.io/sax/) simulations from QUCS?
@flaport
@nikosavola
![image](https://github.com/Qucs/qucs/assets/4514346/02dccd09-256b-421d-9f93-237965ac5f…
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The temp_sensor in OpenFASoC has LVS issue after the update of write_cdl.
Link to OpenFASoC: (https://github.com/idea-fasoc/OpenFASOC)
The power nets in cdl file are unconnected.
![Capture](ht…
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### Description
Hello sir, i want to inject some faults into AES with tool synfi which needs netlist, so i tried to synthsis IP AES with tool dc, the command is below:
`opentitan/hw/ip/aes/syn$ dv…
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Clash 1.6.4 (and 1.6.3) compiled against ghc 8.8.4 on debian unstable synthesizes verilog fine for my code, but 1.6.4 compiled against ghc 9.0.2 fails on the same synthesis. Same machine, same everyth…
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I like the idea of an abstract project model. I have difficulties understanding the concept of how designs and file sets are to be used in the project model and what the difference between a design an…
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I'm running under WSL2, using the most-recent head of the tree (I did the 'git pull' about 5 minutes ago so this looks like the first issue filed on 13.0). I'm also taking a crack at learning SystemV…
wmlye updated
10 months ago