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I request that the following data is removed from The Stack:
- TrechNex/mastodome-legacy
- TrechNex/gimp-macos-build
_Note_: If you don't want all resources to be included just remove the el…
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### Description
With tightly packed macros, LVS fails due to hanging strips of metal on the PDN
![image](https://user-images.githubusercontent.com/634220/165980217-76371dd2-6281-4619-911e-77aaed90…
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Currently we CI seems to only harden the user project macro, it would be nice to also harden the `user_project_wrapper` so that we can also catch regression over the integration with caravel.
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### Description
While instantiating macros, `Odb.SetPowerConnections` in OpenLane2 sometimes fails for some macros.
Based on the logs: Do you have an idea what is happening?
I think the algor…
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1. For the `sky130_sram_macros`, connectivity is extracted incorrectly (unconnected nets) if `cif istyle sky130(vendor)` is specified.
2. If `cif istyle sky130(vendor)` is omitted, top level ports ar…
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Hi, I saw on the official website of OpenRAM that it supports generating multi-port devices, and the displayed bitcell structure supports at least three ports. However, when I tried to generate a thre…
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When I try to run OpenCache on the default config files, I'm getting this error:
```
nachiket in generator git:(dev*) 24-03-14 11:56AM python3 opencache.py tests/configs/config.py
|==============…
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**Describe the bug**
executing like this:
python3 $OPENRAM_HOME/../sram_compiler.py myconfig
but errors like this:
ERROR: file globals.py: line 326: Unable to read configuration file: /home/zcz/…
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We would like to have some automatic way to annotate which Chisel SyncReadMems out of some number of them in our design should be implemented as SRAM cells. Probably this could be solved fairly quickl…
chick updated
2 years ago
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When I run sky130_sram_4kbyte_1rw1r_32x1024_8 it shows me 52 DRC errors and 3 LVS errors, but it was using the default settings just after installing OpenRAM
Git commit id: 31d2d7145b7714e3d1624aba…