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After successfully run helloworld sim (used cmake_configure.riscvfloat.gcc.sh),
I tried to do regression by below command (from https://github.com/pulp-platform/pulpino/blob/master/sw/README.md)
…
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I'm using attributes to set, which tests to perform. Typically I have bunch of tests tagged by user attribute .disabled, and my automatic python script is running all the tests not having this attribu…
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### [EDIT] Summary:
* Non-blocking (`
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Most of configurations in RC is untested. Making RC almost impossible to accept RTL changes to new RV extension from community.
0. Currently Makefile-based testing decoupled Chisel elaboration, FI…
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Minimal example:
```rust
#[test]
fn test() {
let mut sim = Simulation::new();
// TEST_A
sim.add_testbench(move |mut endpoint: Sim| {
let mut x = endpoint.init()?;
…
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Hi,
## The problem
Following the last update, I discovered that some of my testbenches broke and cannot be easily ported to the new SpiBus implementation.
The first problem is that a naming c…
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Do you think you will add support for verilator in the future? http://www.veripool.org/wiki/verilator
Is there a way for me to add it (easily) in the meantime?
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I want to store "GTKWave" save files along with my testbenches, so that I don't have to reconfigure the view all the time.
This is possible by executing `run.py --gtkwave-args "-a .gtkw" ` via comm…
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I think it would help to test the compatibility if the VICE Testbench would be supported.
https://vice-emu.pokefinder.org/wiki/Testbench
But I have no idea if it would be possible testing an FPG…
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> **Describe the bug**
It looks like if I set up a task with the following in the config/task.conf:
```
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verifica…