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There are some parsers for HDL however all of them have some ridiculous weakness.
I would like to use [hdlConvertor](https://github.com/Nic30/hdlConvertor) because I know that the Python dependency…
Nic30 updated
5 years ago
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Hello. I was having a problem in generating the VHDL for the processor using Processor Generator (ProGe). I did the selection of implementations for register files, immediate units, and function unit…
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**What is your question?**
Sometimes I run VSG against code that does not compile i.e. it has VHDL syntax errors. VSG tends to fall over in a heap. Should this happen? Are there not traps somewhere s…
imd1 updated
7 months ago
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As we are separating `clash-cores` from `clash-compiler`, I tried to support not just Clash master but also Clash 1.8. But there are several cores in `clash-cores` that fail their test suite on Clash …
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Hi,
I am trying to simulate de0-nano-test-setup using Questa Intel FPGA Edition but the compilation fails, saying it can't find neorv32_application_image.vhd. The file is definitely in the right pl…
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Hi
I've been experimenting some more with Digital exports to Quartus for compilation/synthesis into a CPLD. This time I am exporting my design to VHDL and importing into Quartus. My project has two…
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Hello, how could I use your schematic viewer to visualize diagrams of VHDL/Verilog hierarchical entities starting from source files?
Thank you and congratulations on your project.
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Hello,
there is a bug I noticed.
It's easy to reproduce following these steps:
1. Open your project-Vhdl-file in vscode.
2. put following simple syntax-error: After end of architecture:
`…
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I'm fairly new to Zed, can somebody tell me how to install this extension and is there a VHDL Language Server or other good extensions available?
Thanks
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After a quick investigation by @glennchid it looks as if component declarations are not required when instantiating Xilinx IP. As there is no other good reason to use component declaration, and they …