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Running `python run.py -x test_report.xml` in [json4vhdl](https://github.com/VUnit/vunit/tree/master/examples/vhdl/json4vhdl) generates an XML that contains 0x0 in the `` tag. However, [most control …
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When interfacing with linters and other tools like LSP's, it would be useful to have some public API to fetch all VUnit source files that should be compiled into `vunit_lib`, including adding `OSVVM` …
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**Describe the bug**
使用iverilog编译时出现错误
---> Build directory: C:Users79458.teroshdlbuild
---> Make installation folder path:
Error: '['make']' exited with an error: 2
**Please complete the fo…
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Without having checked this myself, I believe there is Python code in either [HDLMake](http://www.ohwr.org/projects/hdl-make) or [VUnit](https://github.com/LarsAsplund/vunit) for parsing Verilog/VHDL…
olofk updated
7 years ago
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We want a structured way to write unit tests for the sim.v files (and a way to run them).
We want the unit tests to be compatible with at a minimum;
* Yosys
* Verilator
* Icarus Verilog
Bu…
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Root issue is with a configuration of the following form:
```vhdl
configuration foo_cfg_empty_bah of foo_tb.foo is
for rtl -- foo(rtl)
for u_bar : bar_dsn.bar
for rtl -- bar(rtl)
…
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As commented on gitter:
> @1138-4EB Mar 30 10:05:
>
> About verification components in general, they've been already a year in Beta. Is there any plan to change it in the near future? It would be…
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I noticed a problem with the tool `vunit-test-explorer` (https://github.com/Bochlin/vunit-test-explorer/issues/17). Here you can jump from the GUI to the source code of the test case with one click, w…
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I am new to VUnit and am trying to run through the simple example given in the documentation page. I am running on a Windows 10 platform with cygwin64 installed with the Python 3.8 module. I have Al…
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I have small testbench in conduction with vuinit. This reads an image "test.bin" and the test does nothing than going trough this image and read byte per byte and puts this on an std_logic_vector.
…